Controlling silicon evaporation allows scientists to boost graphene quality

ScienceDaily (Sep. 22, 2011) — Scientists from the Georgia Institute of Technology have for the first time provided details of their "confinement controlled sublimation" technique for growing high-quality layers of epitaxial graphene on silicon carbide wafers. The technique relies on controlling the vapor pressure of gas-phase silicon in the high-temperature furnace used for fabricating the material.

The basic principle for growing thin layers of graphene on silicon carbide requires heating the material to about 1,500 degrees Celsius under high vacuum. The heat drives off the silicon, leaving behind one or more layers of graphene. But uncontrolled evaporation of silicon can produce poor quality material useless to designers of electronic devices.

"For growing high-quality graphene on silicon carbide, controlling the evaporation of silicon at just the right temperature is essential," said Walt de Heer, a professor who pioneered the technique in the Georgia Tech School of Physics. "By precisely controlling the rate at which silicon comes off the wafer, we can control the rate at which graphene is produced. That allows us to produce very nice layers of epitaxial graphene."

De Heer and his team begin by placing a silicon carbide wafer into an enclosure made of graphite. A small hole in the container controls the escape of silicon atoms as the one-square-centimeter wafer is heated, maintaining the rate of silicon evaporation and condensation near its thermal equilibrium. The growth of epitaxial graphene can be done in a vacuum or in the presence of an inert gas such as argon, and can be used to produce both single layers and multiple layers of the material.

"This technique seems to be completely in line with what people might one day do in fabrication facilities," de Heer said. "We believe this is quite significant in allowing us to rationally and reproducibly grow graphene on silicon carbide. We feel we now understand the process, and believe it could be scaled up for electronics manufacturing."

The technique for growing large-area layers of epitaxial graphene was described this week in the Early Edition of the journal Proceedings of the National Academy of Sciences. The research has been supported by the National Science Foundation through the Georgia Tech Materials Research Science and Engineering Center (MRSEC), the Air Force Office of Scientific Research, and the W.M. Keck Foundation.

The paper also describes a technique for growing narrow graphene ribbons, a process de Heer's group has called "templated growth." That technique, which could be useful for making graphene interconnects, was first described in October 2010 in the journal Nature Nanotechnology.

The templated growth technique involves etching patterns into silicon carbide surfaces using conventional nanolithography processes. The patterns serve as templates directing the growth of graphene structures on portions of the patterned surfaces. The technique forms nanoribbons of specific widths without the use of electron beams or other destructive cutting techniques. Graphene nanoribbons produced with these templates have smooth edges that avoid problems with electron scattering.

Together, the two techniques provide researchers with the flexibility to produce graphene in forms appropriate to different needs, de Heer noted. Large-area sheets of graphene may be grown on both the carbon-terminated and silicon-terminated sides of a silicon carbide wafer, while the narrow ribbons may be grown on the silicon-terminated side. Because of different processing techniques, only one side of a particular wafer can be used.

The Georgia Tech research team -- which includes Claire Berger, Ming Ruan, Mike Sprinkle, Xuebin Li, Yike Hu, Baiqian Zhang, John Hankinson and Edward Conrad -- has so far fabricated structures as narrow as 10 nanometers using the templated growth technique. These nanowires exhibit interesting quantum transport properties.

"We can make very good quantum wires using the templated growth technique," de Heer said. "We can make large structures and devices that demonstrate the Quantum Hall Effect, which is important for many applications. We have demonstrated that templated growth can go all the way down to the nanoscale, and that the properties get even better there."

Development of the sublimation technique arose from efforts to protect the growing graphene from oxygen and other contaminants in the furnace. To address the quality concerns, the research team tried enclosing the wafer in a graphite container from which some silicon gas was permitted to leak out.

"We soon realized that graphene grown in the container was much better than what we had been producing," de Heer recalled. "Originally, we thought it was because we were protecting it from contaminants. Later, we realized it was because we were controlling the evaporation of silicon."

Epitaxial graphene may be the basis for a new generation of high-performance devices that will take advantage of the material's unique properties in applications where higher costs can be justified. Silicon, today's electronic material of choice, will continue to be used in applications where high-performance is not required, de Heer said.

Though researchers are still struggling to design nanometer-scale epitaxial graphene devices that take advantage of the material's unique properties, de Heer is confident that will ultimately be done.

"These techniques allow us to make accurate nanostructures and seem to be very promising for making the nanoscale devices that we need," he said. "While there are serious challenges ahead for using graphene in electronics, we have overcome roadblocks before."

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The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by Georgia Institute of Technology Research News. The original article was written by John Toon.

Note: If no author is given, the source is cited instead.

Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.

View the original article here

Controlling silicon evaporation allows scientists to boost graphene quality

ScienceDaily (Sep. 22, 2011) — Scientists from the Georgia Institute of Technology have for the first time provided details of their "confinement controlled sublimation" technique for growing high-quality layers of epitaxial graphene on silicon carbide wafers. The technique relies on controlling the vapor pressure of gas-phase silicon in the high-temperature furnace used for fabricating the material.

The basic principle for growing thin layers of graphene on silicon carbide requires heating the material to about 1,500 degrees Celsius under high vacuum. The heat drives off the silicon, leaving behind one or more layers of graphene. But uncontrolled evaporation of silicon can produce poor quality material useless to designers of electronic devices.

"For growing high-quality graphene on silicon carbide, controlling the evaporation of silicon at just the right temperature is essential," said Walt de Heer, a professor who pioneered the technique in the Georgia Tech School of Physics. "By precisely controlling the rate at which silicon comes off the wafer, we can control the rate at which graphene is produced. That allows us to produce very nice layers of epitaxial graphene."

De Heer and his team begin by placing a silicon carbide wafer into an enclosure made of graphite. A small hole in the container controls the escape of silicon atoms as the one-square-centimeter wafer is heated, maintaining the rate of silicon evaporation and condensation near its thermal equilibrium. The growth of epitaxial graphene can be done in a vacuum or in the presence of an inert gas such as argon, and can be used to produce both single layers and multiple layers of the material.

"This technique seems to be completely in line with what people might one day do in fabrication facilities," de Heer said. "We believe this is quite significant in allowing us to rationally and reproducibly grow graphene on silicon carbide. We feel we now understand the process, and believe it could be scaled up for electronics manufacturing."

The technique for growing large-area layers of epitaxial graphene was described this week in the Early Edition of the journal Proceedings of the National Academy of Sciences. The research has been supported by the National Science Foundation through the Georgia Tech Materials Research Science and Engineering Center (MRSEC), the Air Force Office of Scientific Research, and the W.M. Keck Foundation.

The paper also describes a technique for growing narrow graphene ribbons, a process de Heer's group has called "templated growth." That technique, which could be useful for making graphene interconnects, was first described in October 2010 in the journal Nature Nanotechnology.

The templated growth technique involves etching patterns into silicon carbide surfaces using conventional nanolithography processes. The patterns serve as templates directing the growth of graphene structures on portions of the patterned surfaces. The technique forms nanoribbons of specific widths without the use of electron beams or other destructive cutting techniques. Graphene nanoribbons produced with these templates have smooth edges that avoid problems with electron scattering.

Together, the two techniques provide researchers with the flexibility to produce graphene in forms appropriate to different needs, de Heer noted. Large-area sheets of graphene may be grown on both the carbon-terminated and silicon-terminated sides of a silicon carbide wafer, while the narrow ribbons may be grown on the silicon-terminated side. Because of different processing techniques, only one side of a particular wafer can be used.

The Georgia Tech research team -- which includes Claire Berger, Ming Ruan, Mike Sprinkle, Xuebin Li, Yike Hu, Baiqian Zhang, John Hankinson and Edward Conrad -- has so far fabricated structures as narrow as 10 nanometers using the templated growth technique. These nanowires exhibit interesting quantum transport properties.

"We can make very good quantum wires using the templated growth technique," de Heer said. "We can make large structures and devices that demonstrate the Quantum Hall Effect, which is important for many applications. We have demonstrated that templated growth can go all the way down to the nanoscale, and that the properties get even better there."

Development of the sublimation technique arose from efforts to protect the growing graphene from oxygen and other contaminants in the furnace. To address the quality concerns, the research team tried enclosing the wafer in a graphite container from which some silicon gas was permitted to leak out.

"We soon realized that graphene grown in the container was much better than what we had been producing," de Heer recalled. "Originally, we thought it was because we were protecting it from contaminants. Later, we realized it was because we were controlling the evaporation of silicon."

Epitaxial graphene may be the basis for a new generation of high-performance devices that will take advantage of the material's unique properties in applications where higher costs can be justified. Silicon, today's electronic material of choice, will continue to be used in applications where high-performance is not required, de Heer said.

Though researchers are still struggling to design nanometer-scale epitaxial graphene devices that take advantage of the material's unique properties, de Heer is confident that will ultimately be done.

"These techniques allow us to make accurate nanostructures and seem to be very promising for making the nanoscale devices that we need," he said. "While there are serious challenges ahead for using graphene in electronics, we have overcome roadblocks before."

Recommend this story on Facebook, Twitter,
and Google +1:

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Story Source:

The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by Georgia Institute of Technology Research News. The original article was written by John Toon.

Note: If no author is given, the source is cited instead.

Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.

View the original article here

Two-state dynamics recorded in glassy silicon

ScienceDaily (June 14, 2011) — Using high-resolution imaging technology, University of Illinois researchers have answered a question that had confounded semiconductor researchers: Is amorphous silicon a glass? The answer? Yes -- until hydrogen is added.

Led by chemistry professor Martin Gruebele, the group published its results in the journal Physical Review Letters.

Amorphous silicon (a-Si) is a semiconductor popular for many device applications because it is inexpensive and can be created in a flexible thin film, unlike the rigid, brittle crystalline form of silicon. But the material has its own unusual qualities: It seems to have some characteristics of glass, but cannot be made the way other glasses are.

Most glasses are made by rapidly cooling a melted material so that it hardens in a random structure. But cooling liquid silicon simply results in an orderly crystal structure. Several methods exist for producing a-Si from crystalline silicon, including bombarding a crystal surface so that atoms fly off and deposit on another surface in a random position.

To settle the debate on the nature of a-Si, Gruebele's group, collaborating with electrical and computer engineering professor Joseph Lyding's group at the Beckman Institute for Advanced Science and Technology, used a scanning tunneling microscope to take sub nanometer-resolution images of a-Si surfaces, stringing them together to make a time-lapse video.

The video shows a lumpy, irregular surface; each lump is a cluster about five silicon atoms in diameter. Suddenly, between frames, one bump seems to jump to an adjoining space. Soon, another lump nearby shifts neatly to the right. Although few of the clusters move, the action is obvious.

Such cluster "hopping" between two positions is known as two-state dynamics, a signature property of glass. In a glass, the atoms or molecules are randomly positioned or oriented, much the way they are in a liquid or gas. But while atoms have much more freedom of motion to diffuse through a liquid or gas, in a glass the molecules or atom clusters are stuck most of the time in the solid. Instead, a cluster usually has only two adjoining places that it can ferry between.

"This is the first time that this type of two-state hopping has been imaged in a-Si," Gruebele said. "It's been predicted by theory and people have inferred it indirectly from other measurements, but this is the first time we're been able to visualize it."

The group's observations of two-state dynamics show that pure a-Si is indeed a glass, in spite of its unorthodox manufacturing method. However, a-Si is rarely used in its pure form; hydrogen is added to make it more stable and improve performance.

Researchers have long assumed that hydrogenation has little to no effect on the random structure of a-Si, but the group's observations show that this assumption is not quite correct. In fact, adding hydrogen robs a-Si of its two-state dynamics and its categorization as a glass. Furthermore, the surface is riddled with signs of crystallization: larger clusters, cracks and highly structured patches.

Such micro-crystalline structure has great implications for the properties of a-Si and how they are studied and applied. Since most research has been conducted on hydrogenated a-Si, Gruebele sees a great opportunity to delve into the largely unknown characteristics of the glassy state.

"In some ways, I think we actually know less about the properties of glassy silicon than we think we do, because a lot of what's been investigated of what people call amorphous or glassy silicon isn't really completely amorphous," Gruebele said. "We really need to revisit what the properties of a-Si are. There could yet be surprises in the way it functions and the kind of things that we might be able to do with it."

Next, the group hopes to conduct temperature-depended studies to further establish the activation barriers, or the energy "humps" that the clusters must overcome to move between positions.

The National Science Foundation supported this work.

Video.

Story Source:

The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by University of Illinois at Urbana-Champaign.

Journal Reference:

S. Ashtekar, G. Scott, J. Lyding, M. Gruebele. Direct Imaging of Two-State Dynamics on the Amorphous Silicon Surface. Physical Review Letters, 2011; 106 (23) DOI: 10.1103/PhysRevLett.106.235501

Note: If no author is given, the source is cited instead.

Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.

View the original article here

Two-state dynamics recorded in glassy silicon

ScienceDaily (June 14, 2011) — Using high-resolution imaging technology, University of Illinois researchers have answered a question that had confounded semiconductor researchers: Is amorphous silicon a glass? The answer? Yes -- until hydrogen is added.

Led by chemistry professor Martin Gruebele, the group published its results in the journal Physical Review Letters.

Amorphous silicon (a-Si) is a semiconductor popular for many device applications because it is inexpensive and can be created in a flexible thin film, unlike the rigid, brittle crystalline form of silicon. But the material has its own unusual qualities: It seems to have some characteristics of glass, but cannot be made the way other glasses are.

Most glasses are made by rapidly cooling a melted material so that it hardens in a random structure. But cooling liquid silicon simply results in an orderly crystal structure. Several methods exist for producing a-Si from crystalline silicon, including bombarding a crystal surface so that atoms fly off and deposit on another surface in a random position.

To settle the debate on the nature of a-Si, Gruebele's group, collaborating with electrical and computer engineering professor Joseph Lyding's group at the Beckman Institute for Advanced Science and Technology, used a scanning tunneling microscope to take sub nanometer-resolution images of a-Si surfaces, stringing them together to make a time-lapse video.

The video shows a lumpy, irregular surface; each lump is a cluster about five silicon atoms in diameter. Suddenly, between frames, one bump seems to jump to an adjoining space. Soon, another lump nearby shifts neatly to the right. Although few of the clusters move, the action is obvious.

Such cluster "hopping" between two positions is known as two-state dynamics, a signature property of glass. In a glass, the atoms or molecules are randomly positioned or oriented, much the way they are in a liquid or gas. But while atoms have much more freedom of motion to diffuse through a liquid or gas, in a glass the molecules or atom clusters are stuck most of the time in the solid. Instead, a cluster usually has only two adjoining places that it can ferry between.

"This is the first time that this type of two-state hopping has been imaged in a-Si," Gruebele said. "It's been predicted by theory and people have inferred it indirectly from other measurements, but this is the first time we're been able to visualize it."

The group's observations of two-state dynamics show that pure a-Si is indeed a glass, in spite of its unorthodox manufacturing method. However, a-Si is rarely used in its pure form; hydrogen is added to make it more stable and improve performance.

Researchers have long assumed that hydrogenation has little to no effect on the random structure of a-Si, but the group's observations show that this assumption is not quite correct. In fact, adding hydrogen robs a-Si of its two-state dynamics and its categorization as a glass. Furthermore, the surface is riddled with signs of crystallization: larger clusters, cracks and highly structured patches.

Such micro-crystalline structure has great implications for the properties of a-Si and how they are studied and applied. Since most research has been conducted on hydrogenated a-Si, Gruebele sees a great opportunity to delve into the largely unknown characteristics of the glassy state.

"In some ways, I think we actually know less about the properties of glassy silicon than we think we do, because a lot of what's been investigated of what people call amorphous or glassy silicon isn't really completely amorphous," Gruebele said. "We really need to revisit what the properties of a-Si are. There could yet be surprises in the way it functions and the kind of things that we might be able to do with it."

Next, the group hopes to conduct temperature-depended studies to further establish the activation barriers, or the energy "humps" that the clusters must overcome to move between positions.

The National Science Foundation supported this work.

Video.

Story Source:

The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by University of Illinois at Urbana-Champaign.

Journal Reference:

S. Ashtekar, G. Scott, J. Lyding, M. Gruebele. Direct Imaging of Two-State Dynamics on the Amorphous Silicon Surface. Physical Review Letters, 2011; 106 (23) DOI: 10.1103/PhysRevLett.106.235501

Note: If no author is given, the source is cited instead.

Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.

View the original article here

First telecommunications wavelength quantum dot laser grown on a silicon substrate

ScienceDaily (June 14, 2011) — A new generation of high-speed, silicon-based information technology has been brought a step closer by researchers in the Department of Electronic and Electrical Engineering at UCL and the London Centre for Nanotechnology. The team's research, published in the journal Nature Photonics, provides the first demonstration of an electrically driven, quantum dot laser grown directly on a silicon substrate (Si) with a wavelength (1300-nm) suitable for use in telecommunications.

Silicon is the most widely used material for the fabrication of active devices in electronics. However, the nature of its atomic structure makes it extremely hard to realise an efficient light source in this material.

As the speed and complexity of silicon electronics increases, it is becoming harder to interconnect large information processing systems using conventional copper electrical interconnects. For this reason the field of silicon photonics (the development of optical interconnects for use with silicon electronics) is becoming increasingly important.

The ideal light source for silicon photonics would be a semiconductor laser, for high efficiency, direct interfacing with silicon drive electronics and high-speed data modulation capability. To date, the most promising approach to a light source for silicon photonics has been the use of wafer bonding to join compound semiconductor laser materials from which lasers can be made to a silicon substrate.

Direct growth of compound semiconductor laser material on silicon would be an attractive route to full integration for silicon photonics. However, the large differences in crystal lattice constant between silicon and compound semiconductors cause dislocations in the crystal structure that result in low efficiency and short operating lifetime for semiconductor lasers.

The UCL group has overcome these difficulties by developing special layers which prevent these dislocations from reaching the laser layer together with a quantum dot laser gain layer. This has enabled them to demonstrate an electrically pumped 1,300 nm wavelength laser by direct epitaxial growth on silicon. In a recent paper in Optics Express (Vol. 19 Issue 12, pp.11381-11386 (2011)) they report an optical output power of over 15 mW per facet at room temperature.

In related work the group, working with device fabrication colleagues at the EPSRC National Centre for III-V Technologies, have demonstrated the first quantum dot laser on a germanium (Ge) substrate by direct epitaxial growth. The laser, reported in Nature Photonics , (DOI: 10.1038/NPHOTON.2011.120, 12 June 2009) is capable of continuous operation at temperatures up to 70 deg. C and has a continuous output power of over 25 mW per facet.

Leader of the epitaxy research that enabled the creation of these lasers and Royal Society University Research Fellow in the UCL Department of Electronic and Electrical Engineering, Dr Huiyun Liu, said: "The use of the quantum dot gain layer offers improved tolerance to residual dislocations relative to conventional quantum well structures. Our work on germanium should also permit practical lasers to be created on the Si/Ge substrates that are an important part of the roadmap for future silicon technology."

Head of the Photonics Group in the UCL Department of Electronic and Electrical Engineering, Principal Investigator in the London Centre for Nanotechnology and Director of the EPSRC Centre for Doctoral Training in Photonic Systems Development, Professor Alwyn Seeds, said: "The techniques that we have developed permit us to realise the Holy Grail of silicon photonics -- an efficient, electrically pumped, semiconductor laser integrated on a silicon substrate. Our future work will be aimed at combining these lasers with waveguides and drive electronics leading to a comprehensive technology for the integration of photonics with silicon electronics."

Story Source:

The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by University College London - UCL.

Journal References:

Huiyun Liu, Ting Wang, Qi Jiang, Richard Hogg, Frank Tutu, Francesca Pozzi, Alwyn Seeds. Long-wavelength InAs/GaAs quantum-dot laser diode monolithically grown on Ge substrate. Nature Photonics, 2011; DOI: 10.1038/nphoton.2011.120Ting Wang, Huiyun Liu, Andrew Lee, Francesca Pozzi, Alwyn Seeds. 13-µm InAs/GaAs quantum-dot lasers monolithically grown on Si substrates. Optics Express, 2011; 19 (12): 11381 DOI: 10.1364/OE.19.011381Huiyun Liu, Ting Wang, Qi Jiang, Richard Hogg, Frank Tutu, Francesca Pozzi, Alwyn Seeds. Long-wavelength InAs/GaAs quantum-dot laser diode monolithically grown on Ge substrate. Nature Photonics, 2011; DOI: 10.1038/nphoton.2011.120

Note: If no author is given, the source is cited instead.

Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.

View the original article here

First telecommunications wavelength quantum dot laser grown on a silicon substrate

ScienceDaily (June 14, 2011) — A new generation of high-speed, silicon-based information technology has been brought a step closer by researchers in the Department of Electronic and Electrical Engineering at UCL and the London Centre for Nanotechnology. The team's research, published in the journal Nature Photonics, provides the first demonstration of an electrically driven, quantum dot laser grown directly on a silicon substrate (Si) with a wavelength (1300-nm) suitable for use in telecommunications.

Silicon is the most widely used material for the fabrication of active devices in electronics. However, the nature of its atomic structure makes it extremely hard to realise an efficient light source in this material.

As the speed and complexity of silicon electronics increases, it is becoming harder to interconnect large information processing systems using conventional copper electrical interconnects. For this reason the field of silicon photonics (the development of optical interconnects for use with silicon electronics) is becoming increasingly important.

The ideal light source for silicon photonics would be a semiconductor laser, for high efficiency, direct interfacing with silicon drive electronics and high-speed data modulation capability. To date, the most promising approach to a light source for silicon photonics has been the use of wafer bonding to join compound semiconductor laser materials from which lasers can be made to a silicon substrate.

Direct growth of compound semiconductor laser material on silicon would be an attractive route to full integration for silicon photonics. However, the large differences in crystal lattice constant between silicon and compound semiconductors cause dislocations in the crystal structure that result in low efficiency and short operating lifetime for semiconductor lasers.

The UCL group has overcome these difficulties by developing special layers which prevent these dislocations from reaching the laser layer together with a quantum dot laser gain layer. This has enabled them to demonstrate an electrically pumped 1,300 nm wavelength laser by direct epitaxial growth on silicon. In a recent paper in Optics Express (Vol. 19 Issue 12, pp.11381-11386 (2011)) they report an optical output power of over 15 mW per facet at room temperature.

In related work the group, working with device fabrication colleagues at the EPSRC National Centre for III-V Technologies, have demonstrated the first quantum dot laser on a germanium (Ge) substrate by direct epitaxial growth. The laser, reported in Nature Photonics , (DOI: 10.1038/NPHOTON.2011.120, 12 June 2009) is capable of continuous operation at temperatures up to 70 deg. C and has a continuous output power of over 25 mW per facet.

Leader of the epitaxy research that enabled the creation of these lasers and Royal Society University Research Fellow in the UCL Department of Electronic and Electrical Engineering, Dr Huiyun Liu, said: "The use of the quantum dot gain layer offers improved tolerance to residual dislocations relative to conventional quantum well structures. Our work on germanium should also permit practical lasers to be created on the Si/Ge substrates that are an important part of the roadmap for future silicon technology."

Head of the Photonics Group in the UCL Department of Electronic and Electrical Engineering, Principal Investigator in the London Centre for Nanotechnology and Director of the EPSRC Centre for Doctoral Training in Photonic Systems Development, Professor Alwyn Seeds, said: "The techniques that we have developed permit us to realise the Holy Grail of silicon photonics -- an efficient, electrically pumped, semiconductor laser integrated on a silicon substrate. Our future work will be aimed at combining these lasers with waveguides and drive electronics leading to a comprehensive technology for the integration of photonics with silicon electronics."

Story Source:

The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by University College London - UCL.

Journal References:

Huiyun Liu, Ting Wang, Qi Jiang, Richard Hogg, Frank Tutu, Francesca Pozzi, Alwyn Seeds. Long-wavelength InAs/GaAs quantum-dot laser diode monolithically grown on Ge substrate. Nature Photonics, 2011; DOI: 10.1038/nphoton.2011.120Ting Wang, Huiyun Liu, Andrew Lee, Francesca Pozzi, Alwyn Seeds. 13-µm InAs/GaAs quantum-dot lasers monolithically grown on Si substrates. Optics Express, 2011; 19 (12): 11381 DOI: 10.1364/OE.19.011381Huiyun Liu, Ting Wang, Qi Jiang, Richard Hogg, Frank Tutu, Francesca Pozzi, Alwyn Seeds. Long-wavelength InAs/GaAs quantum-dot laser diode monolithically grown on Ge substrate. Nature Photonics, 2011; DOI: 10.1038/nphoton.2011.120

Note: If no author is given, the source is cited instead.

Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.

View the original article here

Single-crystal arrays of graphene: Advance in efforts to develop a replacement for silicon in high-performance electronics

ScienceDaily (June 2, 2011) — University of Houston researchers have developed a method for creating single-crystal arrays of the material graphene, an advance that opens the possibility of a replacement for silicon in high-performance computers and electronics.

The work by UH researchers and their collaborators is featured on the cover of the June issue of Nature Materials.

Graphene is a one-atom-thick layer of carbon that was first fabricated in 2004. Single-crystal arrays of the material could be used to create a new class of high-speed transistors and integrated circuits that use less energy than silicon electronics because graphene conducts electricity with little resistance or heat generation.

But the industry needs a reliable and defect-free method for manufacturing large quantities of single crystals of graphene. The development reported in Nature Materials marks a step towards perfecting such a method.

"Using these seeds, we can grow an ordered array of thousands or millions of single crystals of graphene," said Qingkai Yu, the paper's first author. Yu developed the single-crystal growth process at the UH Center for Advanced Materials (CAM), where he was a research assistant professor of electrical and computer engineering.

"We hope the industry will look at these findings and consider the ordered arrays as a possible means of fabricating electronic devices," said Yu, who is now an assistant professor at Texas State University in San Marcos and remains a project leader at CAM.

Yu and Steven Pei, UH professor of electrical and computer engineering and CAM's deputy director, invented the graphene seeded-growth technique that UH patented in 2010.

"There is still a long way to go. However, this development makes the fabrication of integrated circuits with graphene transistors possible. This may actually be the first viable integrated circuit technology based on nano-electronics," Pei said.

Yong P. Chen, an assistant professor of nanoscience and physics at Purdue University, was the paper's co-corresponding author.

At CAM, single-crystal graphene arrays were grown on top of a copper foil inside a chamber containing methane gas using a process called chemical vapor deposition. This process was pioneered by Yu at CAM in 2008 and is now widely accepted as the standard method to create large-area graphene films for potential applications in touch-screen displays, e-books and solar cells.

"Graphene isn't there yet, in terms of high quality mass production like silicon, but this is a very important step in that direction," said Chen, who led the graphene characterization efforts at Purdue.

In addition to Yu and Pei, UH graduate students Wei Wu and Zhihua Su, postdoctoral researchers Zhihong Liu and Peng Peng and assistant professor Jiming Bao along with Chen and nine other researchers from Purdue University, Brookhaven National Laboratory, Argonne National Laboratories and Carl Zeiss SMT Inc. co-authored the paper.

Last year, two scientists received the Nobel Prize in physics for discovering graphene. At that time, Yu was working at CAM to develop ways to produce mass quantities of high-quality graphene.

The findings reported in Nature Materials demonstrated that researchers could control the growth of the ordered arrays. The researchers also were the first to demonstrate the electronic properties of individual grain boundaries.

The research was supported through a variety of funding sources, including the National Science Foundation, the U.S. Department of Energy, the Department of Homeland Security, the Defense Threat Reduction Agency, IBM Inc., the Welch Foundation, the Miller Family Endowment and Midwest Institute for Nanoelectronics Discovery.

Story Source:

The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by University of Houston.

Journal Reference:

Qingkai Yu, Luis A. Jauregui, Wei Wu, Robert Colby, Jifa Tian, Zhihua Su, Helin Cao, Zhihong Liu, Deepak Pandey, Dongguang Wei, Ting Fung Chung, Peng Peng, Nathan P. Guisinger, Eric A. Stach, Jiming Bao, Shin-Shem Pei, Yong P. Chen. Control and characterization of individual grains and grain boundaries in graphene grown by chemical vapour deposition. Nature Materials, 2011; 10 (6): 443 DOI: 10.1038/nmat3010

Note: If no author is given, the source is cited instead.

Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.

View the original article here

Single-crystal arrays of graphene: Advance in efforts to develop a replacement for silicon in high-performance electronics

ScienceDaily (June 2, 2011) — University of Houston researchers have developed a method for creating single-crystal arrays of the material graphene, an advance that opens the possibility of a replacement for silicon in high-performance computers and electronics.

The work by UH researchers and their collaborators is featured on the cover of the June issue of Nature Materials.

Graphene is a one-atom-thick layer of carbon that was first fabricated in 2004. Single-crystal arrays of the material could be used to create a new class of high-speed transistors and integrated circuits that use less energy than silicon electronics because graphene conducts electricity with little resistance or heat generation.

But the industry needs a reliable and defect-free method for manufacturing large quantities of single crystals of graphene. The development reported in Nature Materials marks a step towards perfecting such a method.

"Using these seeds, we can grow an ordered array of thousands or millions of single crystals of graphene," said Qingkai Yu, the paper's first author. Yu developed the single-crystal growth process at the UH Center for Advanced Materials (CAM), where he was a research assistant professor of electrical and computer engineering.

"We hope the industry will look at these findings and consider the ordered arrays as a possible means of fabricating electronic devices," said Yu, who is now an assistant professor at Texas State University in San Marcos and remains a project leader at CAM.

Yu and Steven Pei, UH professor of electrical and computer engineering and CAM's deputy director, invented the graphene seeded-growth technique that UH patented in 2010.

"There is still a long way to go. However, this development makes the fabrication of integrated circuits with graphene transistors possible. This may actually be the first viable integrated circuit technology based on nano-electronics," Pei said.

Yong P. Chen, an assistant professor of nanoscience and physics at Purdue University, was the paper's co-corresponding author.

At CAM, single-crystal graphene arrays were grown on top of a copper foil inside a chamber containing methane gas using a process called chemical vapor deposition. This process was pioneered by Yu at CAM in 2008 and is now widely accepted as the standard method to create large-area graphene films for potential applications in touch-screen displays, e-books and solar cells.

"Graphene isn't there yet, in terms of high quality mass production like silicon, but this is a very important step in that direction," said Chen, who led the graphene characterization efforts at Purdue.

In addition to Yu and Pei, UH graduate students Wei Wu and Zhihua Su, postdoctoral researchers Zhihong Liu and Peng Peng and assistant professor Jiming Bao along with Chen and nine other researchers from Purdue University, Brookhaven National Laboratory, Argonne National Laboratories and Carl Zeiss SMT Inc. co-authored the paper.

Last year, two scientists received the Nobel Prize in physics for discovering graphene. At that time, Yu was working at CAM to develop ways to produce mass quantities of high-quality graphene.

The findings reported in Nature Materials demonstrated that researchers could control the growth of the ordered arrays. The researchers also were the first to demonstrate the electronic properties of individual grain boundaries.

The research was supported through a variety of funding sources, including the National Science Foundation, the U.S. Department of Energy, the Department of Homeland Security, the Defense Threat Reduction Agency, IBM Inc., the Welch Foundation, the Miller Family Endowment and Midwest Institute for Nanoelectronics Discovery.

Story Source:

The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by University of Houston.

Journal Reference:

Qingkai Yu, Luis A. Jauregui, Wei Wu, Robert Colby, Jifa Tian, Zhihua Su, Helin Cao, Zhihong Liu, Deepak Pandey, Dongguang Wei, Ting Fung Chung, Peng Peng, Nathan P. Guisinger, Eric A. Stach, Jiming Bao, Shin-Shem Pei, Yong P. Chen. Control and characterization of individual grains and grain boundaries in graphene grown by chemical vapour deposition. Nature Materials, 2011; 10 (6): 443 DOI: 10.1038/nmat3010

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'Swiss cheese' design enables thin film silicon solar cells with potential for higher efficiencies

ScienceDaily (May 8, 2011) — A bold new design for thin film solar cells that requires significantly less silicon -- and may boost their efficiency -- is the result of an industry/academia collaboration between Oerlikon Solar in Switzerland and the Institute of Physics' photovoltaic group at the Academy of Sciences of the Czech Republic.

One long-term option for low-cost, high-yield industrial production of solar panels from abundant raw materials can be found in amorphous silicon solar cells and microcrystalline silicon tandem cells (a.k.a. Micromorph) -- providing an energy payback within a year.

A drawback to these cells, however, is that the stable panel efficiency is less than the efficiency of presently dominate crystalline wafer-based silicon, explains Milan Vanecek, who heads the photovoltaic group at the Institute of Physics in Prague.

"To make amorphous and microcrystalline silicon cells more stable they're required to be very thin because of tight spacing between electrical contacts, and the resulting optical absorption isn't sufficient," he notes. "They're basically planar devices. Amorphous silicon has a thickness of 200 to 300 nanometers, while microcrystalline silicon is thicker than 1 micrometer."

The team's new design focuses on optically thick cells that are strongly absorbing, while the distance between the electrodes remains very tight. They describe their design in the American Institute of Physics' journal Applied Physics Letters.

"Our new 3D design of solar cells relies on the mature, robust absorber deposition technology of plasma-enhanced chemical vapor deposition, which is a technology already used for amorphous silicon-based electronics produced for liquid crystal displays. We just added a new nanostructured substrate for the deposition of the solar cell," Vanecek says.

This nanostructured substrate consists of an array of zinc oxide (ZnO) nanocolumns or, alternatively, from a "Swiss cheese" honeycomb array of micro-holes or nano-holes etched into the transparent conductive oxide layer (ZnO).

"This latter approach proved successful for solar cell deposition," Vanecek elaborates. "The potential of these efficiencies is estimated within the range of present multicrystalline wafer solar cells, which dominate solar cell industrial production. And the significantly lower cost of Micromorph panels, with the same panel efficiency as multicrystalline silicon panels (12 to 16 percent), could boost its industrial-scale production."

The next step is a further optimization to continue improving efficiency.

Story Source:

The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by American Institute of Physics, via EurekAlert!, a service of AAAS.

Journal Reference:

Milan Vanecek, Oleg Babchenko, Adam Purkrt, Jakub Holovsky, Neda Neykova, Ales Poruba, Zdenek Remes, Johannes Meier, Ulrich Kroll. Nanostructured three-dimensional thin film silicon solar cells with very high efficiency potential. Applied Physics Letters, 2011; 98 (16): 163503 DOI: 10.1063/1.3583377

Note: If no author is given, the source is cited instead.

Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.

View the original article here

'Swiss cheese' design enables thin film silicon solar cells with potential for higher efficiencies

ScienceDaily (May 8, 2011) — A bold new design for thin film solar cells that requires significantly less silicon -- and may boost their efficiency -- is the result of an industry/academia collaboration between Oerlikon Solar in Switzerland and the Institute of Physics' photovoltaic group at the Academy of Sciences of the Czech Republic.

One long-term option for low-cost, high-yield industrial production of solar panels from abundant raw materials can be found in amorphous silicon solar cells and microcrystalline silicon tandem cells (a.k.a. Micromorph) -- providing an energy payback within a year.

A drawback to these cells, however, is that the stable panel efficiency is less than the efficiency of presently dominate crystalline wafer-based silicon, explains Milan Vanecek, who heads the photovoltaic group at the Institute of Physics in Prague.

"To make amorphous and microcrystalline silicon cells more stable they're required to be very thin because of tight spacing between electrical contacts, and the resulting optical absorption isn't sufficient," he notes. "They're basically planar devices. Amorphous silicon has a thickness of 200 to 300 nanometers, while microcrystalline silicon is thicker than 1 micrometer."

The team's new design focuses on optically thick cells that are strongly absorbing, while the distance between the electrodes remains very tight. They describe their design in the American Institute of Physics' journal Applied Physics Letters.

"Our new 3D design of solar cells relies on the mature, robust absorber deposition technology of plasma-enhanced chemical vapor deposition, which is a technology already used for amorphous silicon-based electronics produced for liquid crystal displays. We just added a new nanostructured substrate for the deposition of the solar cell," Vanecek says.

This nanostructured substrate consists of an array of zinc oxide (ZnO) nanocolumns or, alternatively, from a "Swiss cheese" honeycomb array of micro-holes or nano-holes etched into the transparent conductive oxide layer (ZnO).

"This latter approach proved successful for solar cell deposition," Vanecek elaborates. "The potential of these efficiencies is estimated within the range of present multicrystalline wafer solar cells, which dominate solar cell industrial production. And the significantly lower cost of Micromorph panels, with the same panel efficiency as multicrystalline silicon panels (12 to 16 percent), could boost its industrial-scale production."

The next step is a further optimization to continue improving efficiency.

Story Source:

The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by American Institute of Physics, via EurekAlert!, a service of AAAS.

Journal Reference:

Milan Vanecek, Oleg Babchenko, Adam Purkrt, Jakub Holovsky, Neda Neykova, Ales Poruba, Zdenek Remes, Johannes Meier, Ulrich Kroll. Nanostructured three-dimensional thin film silicon solar cells with very high efficiency potential. Applied Physics Letters, 2011; 98 (16): 163503 DOI: 10.1063/1.3583377

Note: If no author is given, the source is cited instead.

Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.

View the original article here

High temperature milestone achieved in silicon spintronics

ScienceDaily (May 9, 2011) — Researchers in the Materials Science and Technology Division of the Naval Research Laboratory have recently demonstrated electrical injection, detection and precession of spin accumulation in silicon, the cornerstone material of modern device technology, at temperatures up to 225 degrees Celsius. These results provide the first demonstration that spin accumulation in Si is viable as a basis for practical devices which meet the operating temperatures specified for commercial (85°C), industrial (100°C) and military (125°C) applications. This is a key enabling step for developing devices which rely on electron spin rather than electron charge, an approach known as semiconductor spintronics that is expected to provide devices with higher performance, lower power consumption and less heat dissipation.

The electron possesses an internal angular momentum called the spin. The International Technology Roadmap for Semiconductors has identified the electron's spin as a new state variable that should be explored as an alternative to the electron's charge for use beyond Moore's Law, a projection named after Intel co-founder Gordon E. Moore. Moore predicted in 1965 that the number of transistors per unit area in an integrated circuit would double approximately every two years as advances in fabrication technology enabled the devices to be made smaller. Although this approach has been remarkably successful, critical device dimensions now approach atomic length scales, so that further size scaling becomes untenable. "Researchers have been forced to look beyond the simple reduction of size to develop future generations of electronic devices," states NRL senior scientist Dr. Berry Jonker. "Electrical generation, manipulation and detection of significant spin polarization in silicon at temperatures that meet commercial and military requirements are essential to validate spin as an alternative to charge for a device technology beyond Moore's Law."

Using ferromagnetic metal / silicon dioxide contacts on silicon, NRL scientists Connie Li, Olaf van 't Erve and Jonker electrically generate and detect spin accumulation and precession in the silicon transport channel at temperatures up to 225°C, and conclude that the spin information can be transported in the silicon over distances readily compatible with existing fabrication technology. They thus overcome a major obstacle in achieving control of the spin variable at temperatures required for practical applications in the most widely utilized semiconductor.

To make a semiconductor spintronic device, one needs contacts that can both generate a current of spin-polarized electrons (called a spin injector), and detect the spin polarization of the electrons (spin detector) in the semiconductor. Because the magnetic contact interface is likely to introduce additional scattering and spin relaxation mechanisms not present in the silicon bulk, the region of the semiconductor directly beneath the contact is expected to be a critical factor in the development of any future spin technology. The NRL scientists probe the spin environment directly under the magnetic metal / silicon dioxide contact using the three terminal geometry illustrated in the accompanying

figure

. Demonstration of spin precession and dephasing in a magnetic field transverse to the injected spin orientation, known as the Hanle effect, is conclusive evidence of spin accumulation, and enables a direct measure of the spin lifetime, a critical parameter for device operation. The NRL researchers observed Hanle precession of the electron spin accumulation in the silicon channel under the contact for biases corresponding to both spin injection and extraction, and determine the corresponding spin lifetimes.

Electronic states can form at the contact interface and introduce deleterious effects for both charge and spin transport. These undesirable states can serve as traps which prevent propagation of either charge or spin in the silicon channel. In bulk silicon, the spin lifetime is known to depend upon the carrier density, and generally decreases as the electron density increases.. "In this study we show that the spin lifetime determined from our measurements changes systematically as one changes carrier concentration of the particular silicon sample used," adds Jonker. "Our results were obtained for a number of different carrier densities and show this trend, thus making it very clear that we obtain spin injection and accumulation in the silicon itself rather than in interface defect states." The result of this research rules out spin accumulation in interface states and demonstrates spin injection, accumulation and precession in the silicon channel.

Story Source:

The above story is reprinted (with editorial adaptations by ScienceDaily staff) from materials provided by Naval Research Laboratory.

Journal Reference:

C.H. Li, O.M.J. van 't Erve, B.T. Jonker. Electrical injection and detection of spin accumulation in silicon at 500 K with magnetic metal/silicon dioxide contacts. Nature Communications, 2011; 2: 245 DOI: 10.1038/ncomms1256

Note: If no author is given, the source is cited instead.

Disclaimer: Views expressed in this article do not necessarily reflect those of ScienceDaily or its staff.

View the original article here